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1 hd61203u (dot matrix liquid crystal graphic display 64-channel common driver) ade-207-274(z) '99.9 rev. 0.0 description the hd61203u is a common signal driver for dot matrix liquid crystal graphic display systems. it generates the timing signals (switch signal to convert lcd waveform to ac, frame synchronous signal) and supplies them to the column driver to control display. it provides 64 driver output lines and the impedance is low enough to drive a large screen. as the hd61203u is produced by a cmos process, it is fit for use in portable battery-driven equipment utilizing the liquid crystal display? low power consumption. the user can easily construct a dot matrix liquid crystal graphic display system by combining the hd61203u and the column (segment) driver hd61202u. features dot matrix liquid crystal graphic display common driver with low impedance low impedance: 1.5 k w max internal liquid crystal display driver circuit: 64 circuits internal dynamic display timing generator circuit display duty cycle ? when used with the column driver hd61202u: 1/48, 1/64, 1/96, 1/128 ? when used with the controller hd61830: selectable out of 1/32 to 1/128 low power dissipation: during displays: 5 mw power supplies: v cc : 2.7~5.5v power supply voltage for liquid crystal display drive: 8v to 16v cmos process 100-pin plastic qfp, 100-pin plastic tqfp, chip
hd61203u 2 ordering information type no. package HD61203UFS 100-pin plastic qfp (fp-100a) hd61203ute 100-pin thin plastic qfp (tfp-100b) hcd61203u chip
hd61203u 3 pin arrangement 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x43 x44 x45 x46 x47 x48 x49 x50 x51 x52 x53 x54 x55 x56 x57 x58 x59 x60 x61 x62 x63 x64 v ee v6r v5r v2r v1r th cl2 cl1 x23 x24 x25 x26 x27 x28 x29 x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 x40 x41 x42 x22 x21 x20 x19 x18 x17 x16 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 v ee v6l v5l v2l v1l v cc dl fs ds1 ds2 c nc r nc cr stb shl gnd nc m/s ? ? nc frm m nc fcs dr ( top view ) HD61203UFS (fp-100a)
hd61203u 4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x45 x46 x47 x48 x49 x50 x51 x52 x53 x54 x55 x56 x57 x58 x59 x60 x61 x62 x63 x64 v ee v6r v5r v2r v1r x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 x40 x41 x42 x43 x44 x19 x18 x17 x16 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 v ee v6l v5l v2l v1l v cc dl fs ds1 ds2 c nc r nc cr stb shl gnd nc m/s ? ? nc frm m nc fcs dr cl1 cl2 th (top view) hd61203utfia (tfp-100b)
hd61203u 5 pad arrangement chip size : 3.40 4.08 m m 2 coordinate : pad center origin : chip center pad size : 90 90 m 2 no.1 no.29 no.28 type code hd61203u no.2 no.52 no.79 no.54 no.78 pad name coordinate xy coordinate xy coordinate xy pad name pad name 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 51 52 53 54 55 56 57 58 59 60 76 77 78 79 80 81 82 83 84 85 61 62 63 64 65 66 67 68 69 70 86 87 88 89 90 91 92 93 94 95 71 72 73 74 75 96 97 98 99 100 1 x21 x20 x19 x18 x17 x16 x15 x14 x50 x49 x48 x47 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 x40 x41 x42 x43 x44 x45 x46 ?513 1712 1544 1385 1238 1091 952 822 692 562 432 302 172 42 ?8 ?18 ?49 ?79 ?09 ?39 ?69 ?99 ?129 ?259 ?389 ?527 ?665 ?821 ?853 ?853 ?828 ?213 ?76 ?46 ?16 ?86 ?56 ?96 ?5 65 195 325 455 585 715 853 1407 ?828 ?522 ?374 ?236 ?097 ?67 ?37 ?07 ?77 ?47 ?17 ?87 ?7 73 203 333 463 593 723 853 983 1122 1261 1399 1513 1513 1513 1513 1513 1546 1693 1853 1853 1470 1304 1170 1040 910 779 649 519 ? ?31 ?61 ?91 ?21 ?51 ?81 ?11 ?041 ?171 ?301 ?479 1513 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 ?513 ?513 ?375 ?828 ?828 ?828 ?828 ?828 ?828 ?828 ?828 ?828 ?828 ?828 ?828 ?828 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 ?513 pad no. pad no. pad no. x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 v6l v5l v2l v1l dl fs ds1 ds2 c r cr shl gnd m/s phi2 phi1 frm m fcs dr cl2 v1r v2r v5r v6r x64 x63 x62 x61 x60 x59 x58 x57 x56 x55 x54 x53 x52 x51 389 259 129 1853 1853 1853 v ee1 v cc v ee2 pad location coordinates
hd61203u 6 block diagram logic logic logic logic 64 63 62 12 64 output terminals liquid crystal display driver circuits bidirectional shift register timing generation circuit oscillator dr fcs m cl2 frm v cc gnd v ee cl1 th dl shl stb rcr r f c f c m/s fs ds1 ds2 ? ? v1l v5l x1 x2 v2l v6l x62 x63 x64 v1r v2r v5r v6r
hd61203u 7 block functions oscillator the cr oscillator generates display timing signals and operating clocks for the hd61202u. it is required when the hd61203u is used with the hd61202u. an oscillation resister rf and an oscillation capacitor cf are attached as shown in figure 1. when using an external clock, input the clock into terminal cr and don? connect any lines to terminals r and c. the oscillator is not required when the hd61203u is used with the hd61830. then, connect terminal cr to the high level and don? connect any lines to terminals r and c (figure 2). r cr c rcrc rf cf open open external clock figure 1 oscillator connection with hd61202u rcrc open open v cc figure 2 oscillator connection with hd61830
hd61203u 8 timing generator circuit the timing generator circuit generates display timing and operating clock for the hd61202u. this circuit is required when the hd61203u is used with the hd61202u. connect terminal m/s to high level (master mode). it is not necessary when the display timing signal is supplied from other circuits, for example, from hd61830. in this case connect the terminals fs, ds1, and ds2 to high level and m/s to low level (slave mode). bidirectional shift register a 64-bit bidirectional shift register. the data is shifted from dl to dr when shl is at high level and from dr to dl when shl is at low level. in this case, cl2 is used as shift clock. the lowest order bit of the bidirectional shift register, which is on the dl side, corresponds to x1 and the highest order bit on the dr side corresponds to x64. liquid crystal display driver circuit the combination of the data from the shift register with the m signal allows one of the four liquid crystal display driver levels v1, v2, v5 and v6 to be transferred to the output terminals (table 1). table 1 output levels data from the shift register m output level 11v2 01v6 10v1 00v5
hd61203u 9 hd61203u terminal functions terminal name number of terminals i/o connected to functions v cc gnd v ee 1 1 2 power supply v cc ?nd: power supply for internal logic. v cc ? ee : power supply for driver circuit logic. v1l, v2l v5l, v6l v1r, v2r v5r, v6r 8 power supply liquid crystal display driver level power supply. v1l (v1r), v2l (v2r): selected level v5l (v5r), v6l (v6r): non-selected level voltages of the level power supplies connected to v1l and v1r should be the same. (this applies to the combination of v2l & v2r, v5l & v5r and v6l & v6r respectively.) m/s 1 i v cc or gnd selects master/slave. m/s = v cc : master mode when the hd61203u is used with the hd61202u, timing generation circuit operates to supply display timing signals and operation clock to the hd61202u. each of i/o common terminals dl, dr, cl2, and m is in the output state. m/s = gnd: slave mode the timing operation circuit stops operating. the hd61203u is used in this mode when combined with the hd61830. even if combined with the hd61202u, this mode is used when display timing signals (m, data, cl2, etc.) are supplied by another hd61203u in the master mode. terminals m and cl2 are in the input state. when shl is v cc , dl is in the input state and dr is in the output state. when shl is gnd, dl is in the output state and dr is in the input state. fcs 1 i v cc or gnd selects shift clock phase. fcs = v cc shift register operates at the rising edge of cl2. select this condition when hd61203u is used with hd61202u or when ma of the hd61830 connects to cl2 in combination with the hd61830. fcs = gnd shift register operates at the fall of cl2. select this condition when cl1 of hd61830 connects to cl2 in combination with the hd61830.
hd61203u 10 terminal name number of terminals i/o connected to functions fs 1 i v cc or gnd selects frequency. when the frame frequency is 70 hz, the oscillation frequency should be: f osc = 430 khz at fcs = v cc f osc = 215 khz at fcs = gnd this terminal is active only in the master mode. connect it to v cc in the slave mode. ds1, ds2 2 i v cc or gnd selects display duty factor. display duty factor 1/48 1/64 1/96 1/128 ds1 gnd gnd v cc v cc ds2 gnd v cc gnd v cc these terminals are valid only in the master mode. connect them to v cc in the slave mode. stb th cl1 1 1 1 iv cc or gnd input terminal for testing connect to stb v cc . connect th and cl1 to gnd. cr, r, c 3 oscillator in the master mode, use these terminals as shown below: rcrcrcrc rf cf open open external clock internal oscillation external clock in the slave mode, stop the oscillator as shown below: rcrc open open v cc ?, ? 2 o hd61202u operating clock output terminals for the hd61202u master mode connect these terminals to terminals ? and ? of the hd61202u respectively. slave mode don? connect any lines to these terminals.
hd61203u 11 terminal name number of terminals i/o connected to functions frm 1 o hd61202u frame signal master mode connect this terminal to terminal frm of the hd61202u. slave mode don? connect any lines to this terminal. m 1 i/o mb of hd61830 or m of hd61202u signal to convert lcd driver signal into ac master mode: output terminal connect this terminal to terminal m of the hd61202u. slave mode: input terminal connect this terminal to terminal mb of the hd61830. cl2 1 i/o cl1 or ma of hd61830 or cl of hd61202u shift clock master mode: output terminal connect this terminal to terminal cl of the hd61202u. slave mode: input terminal connect this terminal to terminal cl1 or ma of the hd61830. dl, dr 2 i/o open or flm of hd61830 data i/o terminals of bidirectional shift register dl corresponds to x1? side and dr to x64? side. master mode output common scanning signal. don? connect any lines to these terminals normally. slave mode connect terminal flm of the hd61830 to dl (when shl = v cc ) or dr (when shl = gnd). m/s v cc gnd shl v cc gnd v cc gnd dl output output input output dr output output output input nc 5 open not used. don? connect any lines to this terminal. shl 1 i v cc or gnd selects shift direction of bidirectional shift register. shl shift direction common scanning direction v cc dl ? dr x1 ? x64 gnd dl ? dr x1 ? x64
hd61203u 12 terminal name number of terminals i/o connected to functions x1?64 64 o liquid crystal display liquid crystal display driver output output one of the four liquid crystal display driver m data output level 10 1010 v2 v6 v1 v5 when shl is v cc , x1 corresponds to com1 and x64 corresponds to com64. when shl is gnd, x64 corresponds to com1 and x1 corresponds to com64.
hd61203u 13 example of application hd61203u connection list m/s th cl1 fcs fs ds1 ds2 stb cr r c ? ? frm m cl2 shl dl dr x1?64 allll hhhhh f rom mb of from cl1 of h from flm of com1?om64 hd61830 hd61830 hd61830 l from flm of com64?om1 hd61830 bl l l hhhhhh f rom mb of from ma of h from flm of to dl/dr of com1?om64 hd61830 hd61830 hd61830 hd61203u no. 2 l to dl/dr from flm of com64?om1 of hd61203u hd61830 no. 2 cl l l hhhhhh f rom mb of from ma of h from dl/dr com65?om128 hd61830 hd61830 of hd61203u no. 1 l from dl/dr com128?om65 of hd61203u no. 1 d h l l h h l l h rf rf cf to ? of to ? of to frm of to m of to cl of h com1?om64 or hd61202u hd61202u hd61202u hd61202u hd61202u lh cf l com64?om1 e h l l h h l l h rf rf cf to ? of to ? of to frm of to m of to cl of h to dl/dr com1?om64 or hd61202u hd61202u hd61202u hd61202u hd61202u of hd61203u l h cf hd61203u to cl2 of no. 2 hd61203u l to dl/dr com64?om1 of hd61203u no. 2 f l l l hhhhhh f rom m of from cl2 of h from dl/dr com1?om64 hd61203u hd61203u of hd61203u no. 1 no. 1 no. 1 l from dl/dr com64?om1 of hd61203u no. 1 notes: h: v cc } fixed l: gnd ?means ?pen? rf: oscillation resister cf: oscillation capacitor
hd61203u 14 outline of hd61203u system configuration use with hd61830 1. when display duty ratio of lcd is 1/64 no. 1 com1 com64 lcd no. 1 hd61830 hd61830 lcd no. 1 hd61830 no. 2 com1 com64 com1 com64 upper lower com1 com64 com1 com64 lower upper lcd one hd61203u drives common signals. refer to connection list a. one hd61203u drives common signals for upper and lower panels. refer to connection list a. two hd61203us drive upper and lower panels separately to ensure the quality of display. no. 1 and no. 2 operate in parallel. for both of no. 1 and no. 2, refer to connection list a. 2. when display duty ratio of lcd is from 1/65 to 1/128 no. 1 com1 com128 lcd hd61830 no. 2 no. 1 hd61830 com1 com128 com1 com128 upper lower lcd no. 2 com1 com128 com1 com128 upper lower lcd no. 1 no. 2 no. 3 no. 4 hd61830 two hd61203us connected serially drive common signals. refer to connection list b for no. 1. refer to connection list c for no. 2. two hd61203us connected serially drive upper and lower panels in parallel. refer to connection list b for no. 1. refer to connection list c for no. 2. two sets of hd61203us connected serially drive upper and lower panels in parallel to ensure the quality of display. refer to connection list b for no. 1 and 3. refer to connection list c for no. 2 and 4.
hd61203u 15 use with hd61202 (1/64 duty ratio) no. 1 com1 com64 lcd hd61202u lcd com1 com64 com1 com64 upper lower com1 com64 com1 com64 lower upper lcd one hd61203u drives common signals and supplies timing signals to the hd61202us. refer to connection list d. one hd61203u drives upper and lower panels and supplies timing signals to the hd61202us. refer to connection list d. two hd61203us drive upper and lower panels in parallel to ensure the quality of display. no. 1 supplies timing signals to no. 2 and the hd61202us. refer to connection list e for no. 1. refer to connection list f for no. 2. no. 1 hd61202u hd61202u no. 1 hd61202u hd61202u no. 2
hd61203u 16 connection example 1 use with hd61202u (ram type segment driver) 1. 1/64 duty ratio (see connection list d) + + r3 v1 r3 v6 r3 v3 r3 v4 r3 v5 r3 v2 v ee contrast open open v cc + + +5v (v cc ) r1 r1 r2 r1 r1 ?0v 0v x1 (x64) m cl2 frm ? ? x64 (x1) shl ds1 ds2 th cl1 fs m/s fcs stb c cr r cf rf v cc v1l, v1r v6l, v6r v5l, v5r v2l, v2r v ee gnd dl dr r3 = 15 w ( ) is at shl = low com1 com64 lcd panel hd61203u m cl frm ? ? hd61202u v1l, v1r v3l, v3r v4l, v4r v2l, v2r v cc gnd v ee v1 v3 v4 v2 v cc gnd v ee note: the values of r1 and r2 vary with the lcd panel used. when bias factor is 1/9, the values of r1 and r2 should satisfy r1 4r1 + r2 = 1 9 for example, r1 = 3 k w , r2 = 15 k w figure 3 example 1
hd61203u 17 ? cl2 dl (dr) c ? ? cl2 frm dl (dr) dr (dl) m x 1 (x64) x 2 (x63) 1 2 3 63 64 1 2 3 63 64 1 * * * * * * 1 frame 1 frame v6 v6 v5 v1 v1 v5 v5 v2 v6 v6 v2 v6 v5 v1 123 47 48 49 ( ): at shl = low note: * phase difference between dl (dr) and cl2 figure 4 example 1 waveform (ram type, 1/64 duty cycle)
hd61203u 18 connection example 2 use with hd61830 (display controller) 1. 1/64 duty ratio (see connection list a) open v cc open v cc v1 v6 v5 v2 v ee gnd open open open see connection example v cc open x1 (x64) m cl2 dl (dr) dr (dl) x64 (x1) shl ds1 ds2 th cl1 fs m/s fcs stb com1 com64 lcd panel hd61203u m cl1 flm hd61830 (display controller) c cr r v cc v1l, v1r v6l, v6r v5l, v5r v2l, v2r v ee gnd frm ? ? ( ) is at shl = low figure 5 example 2 (1/64 duty ratio)
hd61203u 19 1 frame 1 frame 1234 64123 641 v6 v1 v5 v1 v6 v5 v5 v6 v6 v2 v6 v2 v1 v5 v5 v2 v6 v1 v5 v2 ( ): at shl = low mb flm cl1 x1 (x64) x2 (x63) x64 (x1) v6 from hd61830 figure 6 example 2 waveform (1/64 duty ratio)
hd61203u 20 2. 1/100 duty ratio (see connection list b, c) v cc v cc com1 com64 com65 com100 lcd panel shl ds1 ds2 th cl1 fs m/s fcs stb x1 (x64) x64 (x1) x1 (x64) x36 (x29) shl ds1 ds2 th cl1 fs m/s fcs stb v cc v1l, v1r v6l, v6r v5l, v5r v2l, v2r v ee gnd v cc open open r cr c m cl2 dl (dr) dr (dl) hd61203u (master) no. 1 m cl2 dl (dr) dr (dl) open hd61203u (slave) no. 2 v cc v1l, v1r v6l, v6r v5l, v5r v2l, v2r v ee gnd c cr r open open v cc flm ma mb hd61830 display controller see connection example 1 v cc v1 v6 v5 v2 v ee gnd note: ( ) is at shl = low figure 7 example 2 (1/100 duty ratio)
hd61203u 21 1 frame 1 frame 12 100 3646566 100 123 646566 100 12 v6 v1 v5 v6 v6 v2 v5 v5 v5 v6 v1 v5 v1 v5 v1 v6 v6 v6 v2 v6 v2 v2 v1 v5 v5 v5 v2 mb flm ma dr(dl) hd61203u no. 1 x1 (x64) x64 (x1) x1 (x64) x36 (x29) hd61830 hd61203u no. 1 hd61203u no. 2 figure 8 example 2 waveform (1/100 duty ratio)
hd61203u 22 absolute maximum ratings item symbol limit unit notes power supply voltage (1) v cc ?.3 to +7.0 v 2 power supply voltage (2) v ee v cc ?17.0 to v cc + 0.3 v 5 terminal voltage (1) v t1 ?.3 to v cc + 0.3 v 2, 3 terminal voltage (2) v t2 v ee ?0.3 to v cc + 0.3 v 4, 5 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: 1. if lsis are used beyond absolute maximum ratings, they may be permanently destroyed. we strongly recommend you to use the lsi within electrical characteristic limits for normal operation, because use beyond these conditions will cause malfunction and poor reliability. 2. based on gnd = 0v. 3. applies to input terminals (except v1l, v1r, v2l, v2r, v5l, v5r, v6l, and v6r) and i/o terminals at high impedance. 4. applies to v1l, v1r, v2l, v2r, v5l, v5r, v6l, and v6r. 5. apply the same value of voltages to v1l and v1r, v2l and v2r, v5l and v5r, v6l and v6r, v ee (23 pin) and v ee (58 pin) respectively. maintain v cc 3 v1l = v1r 3 v6l = v6r 3 v5l = v5r 3 v2l = v2r 3 v ee
hd61203u 23 electrical characteristics dc characteristics (v cc = 2.7v to 5.5v, gnd = 0v, v cc ? ee = 8.0 to 16.0v, ta = ?0 to +75 c) *14 specifications test item symbol min typ max unit test conditions notes input high voltage v ih 0.7 v cc ? cc v1 input low voltage v il gnd 0.3 v cc v1 output high voltage v oh v cc ?0.4 v i oh = ?.4 ma 2 output low voltage v ol 0.4 v i ol = 0.4 ma 2 vi?j on resistance r on 1.5 k w v cc ? ee = 10v load current 150 m a 13 input leakage current i il1 ?.0 1.0 m a vin = 0 to v cc 3 input leakage current i il2 ?.0 2.0 m a vin = v ee to v cc 4 operating frequency f opr1 50 600 khz in master mode external clock operation 5 operating frequency f opr2 0.5 1500 khz in slave mode shift register 6 oscillation frequency f osc 315 450 585 khz cf = 20 pf 5% rf = 39 k w 2% 7, 12 dissipation current (1) i gg1 1.0 ma in master mode 1/128 duty cycle cf = 20 pf rf = 39 k w 8, 9 dissipation current (2) i gg2 200 m a in slave mode 1/128 duty cycle 8, 10 dissipation current i ee 100 m a in master mode 1/128 duty cycle 8, 11 notes: 1. applies to input terminals fs, ds1, ds2, cr, shl, m/s, and fcs and i/o terminals dl, m, dr and cl2 in the input state. 2. applies to output terminals, ?, ?, and frm and i/o common terminals dl, m, dr, and cl2 in the output status. 3. applies to input terminals fs, ds1, ds2, cr, stb , shl, m/s, fcs, cl1, and th, i/o terminals dl, m, dr, and cl2 in the input state and nc terminals. 4. applies to v1l, v1r, v2l, v2r, v5l, v5r, v6l, and v6r. don? connect any lines to x1 to x64.
hd61203u 24 5. external clock is as follows. th tl t fcp t rcp 0.7 v cc 0.5 v cc 0.3 v cc open open cr r c external clock external clock waveform duty cycle t rcp t fcp min 45 typ 50 max 55 50 50 unit % ns ns duty cycle = th th + tl 100% 6. applies to the shift register in the slave mode. for details, refer to ac characteristics. 7. connect oscillation resistor (rf) and oscillation capacitance (cf) as shown in this figure. oscillation frequency (f osc ) is twice as much as the frequency (f? at ? or ?. cf rf cr r c ?, ? cf = 20 pf rf = 39 k w f osc = 2 f 8. no lines are connected to output terminals and current flowing through the input circuit is excluded. this value is specified at vih = v cc and vil = gnd. 9. this value is specified for current flowing through gnd in the following conditions: internal oscillation circuit is used. each terminal of ds1, ds2, fs, shl, m/s, stb , and fcs is connected to v cc and each of cl1 and th to gnd. oscillator is set as/ described in note 7. 10. this value is specified for current flowing through gnd under the following conditions: each terminals of ds1, ds2, fs, shl, stb , fcs and cr is connected to v cc , cl1, th, and m/s to gnd and the terminals cl2, m, and dl are respectively connected to terminals cl2, m, and dl of the hd61203u under the condition described in note 9. 11. this value is specified for current flowing through v ee under the condition described in note 9. don? connect any lines to terminal v. 12. this figure shows a typical relation among oscillation frequency, rf and cf. oscillation frequency may vary with the mounting conditions. c f = 20 pf 50 100 r f (k w ) 600 400 200 0 f osc (khz)
hd61203u 25 13. resistance between terminal x and terminal v (one of v1l, v1r, v2l, v2r, v5l, v5r, v6l, and v6r) when load current flows through one of the terminals x1 to x64. this value is specified under the following conditions: terminal x (x1 to x64) v1l, v1r v6l, v6r v5l, v5r v2l, v2r ron v cc ? ee = 10v v1l = v1r, v6l = v6r = v cc ?1/7 (v cc ? ee ) v2l = v2r, v5l = v5r = v ee + 1/7 (v cc ? ee ) connect one of the lines the following is a description of the range of power supply voltage for liquid crystal display drive. apply positive voltage to v1l = v1r and v6l = v6r and negative voltage to v2l = v2r and v5l = v5r within the d v range. this range allows stable impedance on driver output (ron). notice that d v depends on power supply voltage v cc ? ee . d v d v v cc v1 (v1l = v1r) v6 (v6l = v6r) v5 (v5l = v5r) v2 (v2l = v2r) v ee 3.5 2 d v (v) 816 v cc ? ee (v) range of power supply voltage for liquid crystal display drive correlation between driver output waveform and power supply voltage for liquid crystal display drive correlation between power supply voltage v cc ? ee and d v 14. specified at +75 c for die products.
hd61203u 26 terminal configuration pmos v cc nmos applicable terminals: cr, m/s, shl, fcs, ds1, ds2, fs applicable terminals: dl, dr, cl2, m i/o terminal input terminal pmos nmos v cc output terminal v cc pmos v1l, v1r v cc pmos v6l, v6r v ee nmos v5l, v5r v ee nmos v2l, v2r applicable terminals: x1 to x64 pmos v cc nmos (input circuit) enable data output circuit (tristate) output terminal pmos nmos v cc applicable terminals: ?, ?, frm
hd61203u 27 ac characteristics (v cc = 2.7v to 5.5v, gnd = 0v, ta = ?0 to +75 c) *2 in the slave mode (m/s = gnd) 0.7 v cc 0.3 v cc t f t r t r t f t ds t dh t wlcl2l t whcl2h t wlcl2h t whcl2l 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t dd t dhw 0.7 v cc 0.3 v cc cl2 (fcs = gnd) (shift clock) cl2 (fcs = v cc ) (shift clock) dl (shl = v cc ) dr (shl = gnd) input data dr (shl = v cc ) dl (shl = gnd) output data item symbol min typ max unit note cl2 low level width (fcs = gnd) t wlcl2l 450 ns cl2 high level width (fcs = gnd) t wlcl2h 150 ns cl2 low level width (fcs = v cc )t whcl2l 150 ns cl2 high level width (fcs = v cc )t whcl2h 450 ns data setup time t ds 100 ns data hold time t dh 100 ns data delay time t dd 200 ns 1 data hold time t dhw 10 ns cl2 rise time t r 30 ns cl2 fall time t f 30 ns notes: 1. the following load circuit is connected for specification. 30 pf (includes jig capacitance) output terminal 2. specified at +75 c for die products.
hd61203u 28 3. in the master mode (m/s = v cc , fcs = v cc , cf = 20 pf, rf = 39 k w ) 0.7 v cc 0.3 v cc t wcl2l t wcl2h t dh t ds t dh t dd t ds 0.7 v cc 0.3 v cc t dd 0.7 v cc 0.3 v cc 0.3 v cc 0.7 v cc t dfrm t dfrm t dm 0.7 v cc 0.3 v cc t w?h t r t f t w?l t f t r t w?h t d21 t d12 t w?l 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc cl2 dl (shl = v cc ) dr (shl = gnd) dr (shl = v cc ) dl (shl = gnd) frm m ? ?
hd61203u 29 item symbol min typ max unit data setup time t ds 20 m s data hold time t dh 40 m s data delay time t dd 5 m s frm delay time t dfrm ? +2 m s m delay time t dm ? +2 m s cl2 low level width t wcl2l 35 m s cl2 high level width t wcl2h 35 m s ? low level width t w?l 700 ns ? low level width t w?l 700 ns ? high level width t w?h 2100 ns ? high level width t w?h 2100 ns ?2 phase difference t d12 700 ns ?1 phase difference t d21 700 ns ?, ? rise time t r 150 ns ?, ? fall time t f 150 ns
hd61203u 30 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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